The present invention relates to a semiconductor integrated circuit device and a manufacture method therefor, and in particular, to a semiconductor integrated circuit device comprising a second-conductivity-type well area on a main surface of a first-conductivity-type semiconductor substrate and a MOSFET formed in a first-conductivity-type well area formed within the second-conductivity-type well area.
The well-known triple-well NMOS transistor has an N-type well area formed on a main surface of a P-type semiconductor substrate, a P-type well area further formed within the N-type well area, and an NMOSFET formed in the P-type well area (Japanese Patent Application Publication No. 7-78881). With the triple-well NMOS transistor, the potentials at a source and a well can be set to be equal, thereby avoiding a back gate bias. Further, in the triple-well NMOS transistor, the NMOS transistor is formed in the P-type well within the N-type well, so that (for example), the N-type well can be set to have the highest potential, while the P-type well can be set to have a lower potential. Consequently, this transistor has the advantage of enabling the use of a negative voltage.
Japanese Patent Application Publication No. 11-233769 discloses a technique of restraining the occurrence of a punch-through phenomenon in a fine MOSFET by forming an impurity area (punch-through stopper area) deep below a gate electrode, the impurity area having a conductivity type opposite to that of a source and a drain. Furthermore, Japanese Patent Application Publication No. 2000-91574 discloses a technique of increasing a drain voltage resistance by forming an offset drain area between a drain area and a channel formed area, the offset drain area having the same conductivity type as the drain area and a lower impurity concentration than the drain area. Moreover, Japanese Patent Application Publication 7-183390 discloses a semiconductor device having a punch-through stopper area and an offset drain area.
However, in the above-described triple-well NMOS transistor, the N-type drain area, the P-type well area, and the N-type well area constitute a parasitic bipolar transistor, so that a parasitic current may flow that corresponds to the amount of injected charge, such as substrate current multiplied by current gain. Such parasitic current may have the adverse effect of increasing current consumption or causing a thermal runaway of the parasitic bipolar transistor, destroying the elements.
It would therefore be desirable to provide a semiconductor integrated circuit device comprising a MOS transistor having a triple-well structure, wherein substrate current can be restrained and the current gain of the parasitic bipolar transistor reduced to prevent an increase in current consumption and the destruction of elements resulting from a thermal runaway of the parasitic bipolar transistor.
It would further be desirable to provide a method of manufacturing a semiconductor integrated circuit device, which method can use as few steps as possible to manufacture an integrated circuit device comprising a MOS transistor having a triple well structure and a conventional fine CMOS transistor formed in a single well, the MOS and CMOS transistors being provided on the same semiconductor substrate.
The present invention provides a semiconductor integrated circuit device comprising a triple-well transistor having a second-conductivity-type well area formed on a main surface of a first-conductivity-type semiconductor substrate, a first-conductivity-type well area further formed within the second-conductivity-type well area, and a MOSFET formed in the first-conductivity-type well area, wherein a drain area is formed apart from a gate electrode, and an impurity-diffused area having a lower impurity concentration than the drain area is formed between the drain area and a drain area side end of the gate electrode.
In the manufacture of this semiconductor integrated circuit device, the second-conductivity-type well area of the triple-well MOS transistor and a second-conductivity-type well area of a fine CMOS transistor are simultaneously formed. Further, the first-conductivity-type well area of the triple-well MOS transistor and a first-conductivity-type well area of the fine CMOS transistor may be simultaneously formed. Furthermore, if the fine CMOS transistor has an LDD area, this LDD area and said impurity-diffused area of the triple-well MOS transistor may be simultaneously formed.
According to the present invention, the impurity-diffused area having a lower impurity concentration than the drain area is formed on the drain side of the triple-well MOS transistor, thereby restraining the substrate current, which may lead to the flow of parasitic current from a parasitic bipolar transistor composed of the second-conductivity-type drain area, the first-conductivity-type well area, and the second-conductivity-type well area. Further, in the triple-well MOS transistor, the current gain of the parasitic bipolar transistor can be reduced by increasing the impurity concentration of the first-conductivity-type well area. Furthermore, an increase in the number of process steps can be minimized by simultaneously forming the impurity-diffused area of the triple-well MOS transistor and the LDD area of the fine CMOS device.